Leakage across a device is one of today's most important VLSI design issues. Leakage is the uncontrolled (“parasitic”) current flowing across region(s) of semiconductor structure/device in which no current should be flowing; e.g., current flowing across the gate oxide in MOS.
In any event, accurate and consistent leakage power estimation is critical at all stages of ASIC design. For example, cell level leakage models are needed to drive optimization tools which would allow the ASIC designer to budget real chip leakage used for power optimization in synthesis. That is, by way of illustration, it would allow the ASIC designer to use slower high threshold cells where timing is not critical and fast, but leakage prone low threshold cells when needed for timing closure. ASIC libraries are made up of cells that are comprised of a combination of transistors and capacitors connected to perform a logic function. The chip netlists describe a collection of these cells, and their connections.
Chip leakage can be estimated based on a chip netlist, using cell models and EDA tools. By way of example, to limit leakage while obtaining performance benefits, the ASIC designer can use tools such as Synopsys Power Compiler™, Cadence RTL Compiler™ or Cadence Encounter™. For example, the ASIC designer can use such tools to obtain the performance benefits of LVt (low voltage threshold) devices, while limiting leakage by using HVt (high voltage threshold) devices on non-critical paths. (It is well known that there is an exponential dependency between Vt and leakage, e.g., HVt devices leak less but are slower, while LVt transistors are faster but leak far more).
The leakage model for each cell, in each Vt variation, must accurately reflect the very large PVT (process, voltage, temperature) dependence. Library characterization using SPICE is, in principle, capable of modeling such leakage; however, SPICE techniques may not be the most appropriate technique for modeling leakage since SPICE models used for library characterization may not reflect effects important for leakage. As should be known, SPICE is a simulation technique used to simulate circuits at a transistor level.
By way of examples, SPICE modeling is typically used for timing closure, whereas, leakage is sensitive to even small process shifts which might be unimportant for timing closure. By way of further example, leakage and its temperature acceleration are functions of full-die Vt distribution, which cannot be reflected in the transistor level SPICE simulation. Moreover, SPICE characterization is not possible for certain categories of library IP. Also, it is difficult to update the SPICE models as the process matures and leakage changes in that full re-characterization of the entire cell library would be needed to address even small process shifts, e.g., Vt (voltage threshold), Tox (oxide thickness), recentering and corner re-definition, to name but a few.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.